Integrated circuits are typically formed using photolithographic processes in which a pattern is projected from a reticle or mask onto a substrate, and then the pattern is etched or otherwise formed into the substrate. This general process is repeated over and over again as additional layers are formed on the substrate, until the integrated circuit is completed.
As the term is used herein, “integrated circuit” includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III-V compounds like gallium arsenide, or mixtures of such materials. The term includes all types of devices formed, such as memory and logic, and all designs of such devices, such as MOS and bipolar. The term also comprehends applications such as flat panel displays, solar cells, and charge coupled devices.
Generally, the photo masks, reticles, templates, electron-beam large-area patterns, and even the production wafers themselves (all generally referred to as substrates herein) are typically formed by stepping smaller blocks of the pattern across the surface of the substrate, and logically stitching these blocks together to form the larger, desired pattern, and then just assuming that these small blocks line up in the desired manner.
In times past, the majority of tooling was intended to be photo reduced by a factor of four, so any stitching errors were typically reduced to about four or five nanometers, which was considered to be negligible. However, with the continued reduction in the size of the critical features of modern integrated circuits, and the advent of 1x tooling such as nano-imprint and x-ray that are not photo reduced, these stitching errors could potentially create a significant problem.
What is needed, therefore, is a system that overcomes problems such as those described above, at least in part.